1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device being capable of holding stored information even if power is shut off.
2. Description of the Related Art
A semiconductor memory device is roughly classified into two categories; so-called a volatile memory in which stored information is erased when power is shut off and also so-called a nonvolatile memory in which stored information is held even when the power is shut off. The former is known as a RAM (Random Access Memory) and the latter as a ROM (Read Only Memory). The ROM, in particular, is employed in a variety of information processing devices thanks to its non-volatility. Of the ROMs, an EPROM (Erasable and Programmable ROM) in which information written once can be erased by the radiation of ultraviolet rays and can be electrically written and/or an EEPROM (Electrically Erasable and Programmable ROM) in which information written once can be electrically erased and can be rewritten are widely used. In particular, the EPROM in which information can be batch-erased and written in bytes is known as a flash memory. This has become a focus of attention as a possible alternative to a floppy disk and/or hard disk which are conventionally typical of a storage medium.
The nonvolatile semiconductor memory device has a MIS (Metal Insulator Semiconductor) type structure. Its metal gate has a stacked structure composed of a floating gate embedded in an insulating film and of a control gate disposed on an insulating body above the floating gate.
To store information in the semiconductor memory device, a comparatively high positive voltage of about 12V is applied between the control gate and a source and a positive voltage of about 6V is applied between the source and a drain to generate a hot electron in an electron flowing from the source to the drain and, by utilizing an F-N (Fowler-Nordheim) tunnel mechanism, to inject the hot electron into the floating gate for charging.
On the other hand, to erase stored information, the F-N tunnel mechanism is again used to discharge electrons from the floating gate. That is, the control gate is grounded or negatively biased to be -8V while the source is positively biased to be 12 to 8V to erase information through the source. As an alternative method, the control gate is negatively biased and the semiconductor substrate is positively biased to erase information through a channel.
Accordingly, since a threshold voltage of a MIS-type transistor differs depending on the existence or absence of electrons at the floating gate, information can be read by detecting the amount of change of the threshold voltage.
FIG. 6 is a top view showing one example of an approximate layout of a conventional semiconductor memory device. The conventional semiconductor memory device has a plurality of unit assemblies 52 containing more than one memory cell (MC) 51, which is surrounded by a broken line in the drawing, disposed in a matrix-like manner in the directions of a word line (X) and of a bit line (Y).
The memory cell 51 has a nonvolatile MIS-type structure with a floating gate and a control gate. The reference number 53a is a first main source line (MSL1), 53b being a second main source line (MSL2), 54a being a first main bit line (MBL1), 54b being a second main bit line (MBL2), 55a being a first sub-source line (SSL1), 55b being a second sub-source line (SSL2), 56a is a first sub-bit line (SBL1), 56b is a second sub-bit line (SBL2), 57a being a first source select transistor (TSS1), 57b being a second source select transistor (TSS2), 58a being a first bit select transistor (TSB1), 58b being a second bit select transistor (TSB2), 59a being a first source contact (CS1), 59b being a second source contact (CS2), 60a being a first bit contact (CB1) and 60b being a second bit contact (CB2).
The first and second main source lines 53a and 53b, and the first and second main bit lines 54a and 54b are all composed of metal wiring made of aluminum or the like. The first and second sub-source lines 55a and 55b, and the first and second sub-bit lines 56a and 56b are composed of diffused layers formed on a semiconductor substrate. The first and second source select transistors 57a and 57b, the first and second bit select transistors 58a and 58b are composed of conventional MIS-type transistors. The first and second source contact 59a and 59b, and the first and second bit contacts 60a and 60b are formed in a contact hole being opened through an insulating film, which serve to make the metal wiring contact to the diffused layer.
The first and second source select transistors 57a and 57b are adapted to independently control the first and second source line 55a and 55b in order to write, delete and read information. Similarly, the first and second bit select transistors 58a and 59b are adapted to independently control the first and second sub-bit line 56a and 56b in order to write, delete and write information as well.
As depicted in FIG. 6, the unit assembly 52 is so configured that two groups of memory cells 51 consisting one group (first group) having two or more memory cells connected in parallel between the first sub-source line 55a and the first sub-bit line 56a and the other group (second group) having two or more memory cells connected in parallel between the second sub-source line 55b and the second sub-bit line 56b are disposed in a manner that an isolated area 61 is located between these two groups of memory cells.
The first and second sub-bit lines 56a and 56b are elongated along the direction of the bit line (Y) and in one direction (in the downward direction in this example) and are connected to the first and second main bit lines 54a and 54b through the first and second bit contacts 60a and 60b.
On the other hand, the first and second sub-source lines 55a and 55b are elongated along the direction of the bit line and in the other direction (in the upward direction in this example) and are connected to the first and second main source lines 53a and 53b through the first and second source select transistors 57a and 57b and further through the first and second source contacts 59a and 59b. A plurality of unit assemblies 52 described above is disposed in a mirror-image manner in upward and downward as well as right and left places to construct one memory array.
In the conventional semiconductor memory device as shown in FIG. 6, since the first and second bit select transistors 58a and 58b are so disposed that they are adjacent to each other, their sizes are limited from the viewpoint of space. It is, therefore, impossible to make these transistors 58a and 58b larger in size, thus making it difficult to improve their driving capability.
This means that, if all wiring pitches are provided in accordance with the minimum design standard F, the designing is subject to the constraint that these two bit select transistors 58a and 58b must be disposed within an area 6F from the viewpoint of design rules. Moreover, if the bit select transistors 58a and 58b are made larger in size in an attempt to improve their driving capability, the area of the unit assembly 52 increases, as a result, making the whole memory cell array larger in size. The conventional semiconductor memory device has another shortcoming that, due to the use of the metal wiring, a pitch is severely tight in the wiring for the first and second sub-source lines 55a and 55b, and the first and second sub-bit lines 56a and 56b.
A semiconductor memory device which has overcome the above shortcoming is disclosed, for example, in Japanese Patent Application Laid-open Hei 6-283721. FIG. 7 is a top view showing another example of an approximate layout of the semiconductor memory device shown in the above application. FIG. 8 is a top view showing a wiring pattern of the semiconductor device. The semiconductor memory device disclosed in this application differs greatly from that shown in FIG. 6 in that a main source line (MSL) 62 is disposed in the direction of a word line (X) without the use of the first and second main source lines 53a and 53b as shown in FIG. 6 in an approximately same manner as for the wiring of diffused layers in first and second sub-source lines 55a and 55b (or first and second sub-bit lines 56a and 56b). This main source line 62 is connected to the first and second sub-source lines 55a and 55b at the end of an array. This configuration can provide sufficient space to place the first and second bit select transistors 58a and 58b because there is no need to mount the first and second main source lines 53a and 53b, thus allowing the transistors 58a and 58b being larger in size to be mounted.
However, there is another problem in the above conventional semiconductor memory device as disclosed in the application. That is, since the resistance of the first and second sub-bit lines has become high in the structure of the semiconductor memory device disclosed in the above application, the swinging in the potential of the first and second sub-source lines is large. This high resistance of the first and second sub-bit lines is attributable to the wiring constructed by diffused layers. Accordingly, the high resistance causes swinging in the potential of the first and second sub-source lines 55a and 55b. As a result, this leads to inexact operations of the semiconductor memory device when information is to be written, deleted and read out, thus reducing reliability of the memory device.